FPGA Implementation of Low Complexity Decoder Using LDPC Codes (Record no. 30235)

000 -LEADER
fixed length control field 00437nam a2200133Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 180620b2013 xxu||||| |||| 00| 0 eng d
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621 YAD
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Yadav, Sandeep
245 ## - TITLE STATEMENT
Title FPGA Implementation of Low Complexity Decoder Using LDPC Codes
Statement of responsibility, etc. Sandeep Yadav
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Solan [H P]
Name of publisher, distributor, etc. Jaypee University of Information Technology
Date of publication, distribution, etc. 2013
300 ## - PHYSICAL DESCRIPTION
Extent v, 61p.
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Jain, Shruti
906 ## - LOCAL DATA ELEMENT F, LDF (RLIN)
a 4154705fac10491064bc39c48874f1c0
Holdings
Withdrawn status Lost status Damaged status Not for loan Collection code Home library Current library Date acquired Source of acquisition Serial Enumeration / chronology Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type
        PROJECT REPORT SECTION LRC_JUIT LRC_JUIT 14/06/2013 Jaypee University of Information Technology, Solan Copy 1   SPR 621 YAD SPM1338 21/05/2019 21/05/2019 M Tech DISSERTATION

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