VLSI Architecture Design for MD5 Hashing Algorithm (Record no. 76531)

000 -LEADER
fixed length control field 00597nam a2200193Ia 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20241115154638.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 240509s9999 xx 000 0 und d
040 ## - CATALOGING SOURCE
Transcribing agency JUIT, Solan
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621 SON
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Soni, Abhinav
245 #0 - TITLE STATEMENT
Title VLSI Architecture Design for MD5 Hashing Algorithm
Statement of responsibility, etc. by Abhinav Soni, Anirudh Mehrotra and Kushagra Goyal
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Solan
Name of publisher, distributor, etc. Jaypee University of Information Technology
Date of publication, distribution, etc. 2015
300 ## - PHYSICAL DESCRIPTION
Accompanying material PDF
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronics & Communication Engineering
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Mehrotra, Anirudh
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Goyal, Kushagra
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type B. Tech. E - Project Reports
Source of classification or shelving scheme
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Collection code Home library Current library Date acquired Source of acquisition Full call number Barcode Date last seen Copy number Price effective from Koha item type Public note
          PROJECT REPORT SECTION LRC_JUIT LRC_JUIT 09/05/2024 Jaypee University of Information Technology, Solan 621 SON EPR1115177 09/05/2024 Copy 1 09/05/2024 B. Tech. E - Project Reports Guided by Akhil Ranjan

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