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Floating Gate Devices: operation and compact modeling by Paolo Pavan

By: Pavan, PaoloContributor(s): Marmiroli, Andrea | Larcher, LucaMaterial type: Text

TextPublication details: Boston Kluwer Academic Publishers 2004Description: xiii, 129pISBN: 9781402077319Subject(s): Gate array circuits | Flash memories (Computers)DDC classification: 004.53 PAV

Contents:

Table of Contents: 1. Introd

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Item type	Current library	Collection	Call number	Vol info	Status	Date due	Barcode	Item holds
REFERENCE BOOK	LRC_JUIT Electronics & Communication Engineering	REFERENCE SECTION	REF 004.53 PAV (Browse shelf (Opens below))	Copy 1	Not for loan		029987

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Previous	REF 004.22 PLA Dynamically Reconfigurable Systems: architectures, design methods and applications	REF 004.24 HAV Performability Modelling: techniques and tools	REF 004.3 SCH Optimized ASIP Synthesis from Architecture Description Language Models	REF 004.53 PAV Floating Gate Devices: operation and compact modeling	REF 004.6 COS Complex Networks: Second International Workshop, Complenet 2010, Rio de Janeiro, Brazil, October 13-15, 2010, revised selected papers	REF 004.6 DAS Multimedia Communications and Networking	REF 004.6 KIS Mathematics of Epidemics on Networks: from exact to approximate models	Next

Table of Contents:

1. Introd

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