Offset Reduction Technologies in High Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs by Pedro M. Figueiredo
Material type:
TextPublication details: Netherlands Springer Verlag, Netherlands 2009Description: xx, 382pISBN: 1402097158Subject(s): Analog-to-digital convertersDDC classification: 621.38159 FIG
Contents:
Contents:
1. High-speed ADC architectur
| Item type | Current library | Collection | Call number | Vol info | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|
REFERENCE BOOK
|
LRC_JUIT Electronics & Communication Engineering | REFERENCE SECTION | REF 621.38159 FIG (Browse shelf (Opens below)) | Copy 1 | Not for loan | 023148 |
Total holds: 0
Browsing LRC_JUIT shelves, Shelving location: Electronics & Communication Engineering, Collection: REFERENCE SECTION Close shelf browser (Hides shelf browser)
|
|
|
|
|
|
|
||
| REF 621.3815486 LAC Integrated Frequency Synthesizers for Wireless Systems | REF 621.3815486 MCM Automated Calibration of Modulated Frequency Synthesizers | REF 621.3815486 VAU Architectures for RF Frequency Synthesizers | REF 621.38159 FIG Offset Reduction Technologies in High Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs | REF 621.38159 HAR Smart AD and DA Converters | REF 621.38159 MAR The Switching Function: analysis of power electronic circuits | REF 621.382 AND Mobile Media and Applications- from Concept to Cash : successful service creation and launch |
Contents:
1. High-speed ADC architectur
There are no comments on this title.