Power Constrained Testing of VLSI Circuits by Nicola Nicolici
Material type:
TextPublication details: Boston Kluwer Academic Publishers 2003Description: xi, 178p.: ill.; 25 cmISBN: 140207235XSubject(s): Semiconductors -- Thermal properties | Integrated circuits -- Very large scale integration -- Protection | Integrated circuits -- Very large scale integration -- TestingDDC classification: 621.395 NIC
Contents:
Table Of Contents:
1. Design and Test o
| Item type | Current library | Collection | Call number | Vol info | Status | Date due | Barcode | Item holds |
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REFERENCE BOOK
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LRC_JUIT Electronics & Communication Engineering | REFERENCE SECTION | REF 621.395 NIC (Browse shelf (Opens below)) | Copy 1 | Not for loan | 020282 |
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| REF 621.395 MAT Metamodeling-driven IP Reuse for SoC Integration and Microprocessor Design | REF 621.395 MOH VLSI Analog Filters: active RC, OTA-C, and SC | REF 621.395 MOL Interconnection Noise in VLSI Circuits | REF 621.395 NIC Power Constrained Testing of VLSI Circuits | REF 621.395 PER Precision Temperature Sensors in CMOS Technology | REF 621.395 RAM Digital VLSI Systems Design: a design manual for implementation of Projects on FPGAs and ASICs using Verilog | REF 621.395 RAS System-On-A-Chip Verification : methodology and Techniques |
Table Of Contents:
1. Design and Test o
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