FPGA Implementation of Low Complexity Decoder Using LDPC Codes Sandeep Yadav
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TextPublication details: Solan [H P] Jaypee University of Information Technology 2013Description: v, 61pDDC classification: 621 YAD
| Item type | Current library | Collection | Call number | Vol info | Status | Date due | Barcode | Item holds |
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M Tech DISSERTATION
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LRC_JUIT | PROJECT REPORT SECTION | SPR 621 YAD (Browse shelf (Opens below)) | Copy 1 | Not for loan | SPM1338 |
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