OPAC_KOHA catalog › Details for: FPGA Implementation of Low Complexity Decoder Using LDPC Codes

Normal view MARC view ISBD view

FPGA Implementation of Low Complexity Decoder Using LDPC Codes Sandeep Yadav

By: Yadav, SandeepContributor(s): Jain, ShrutiMaterial type: Text

TextPublication details: Solan [H P] Jaypee University of Information Technology 2013Description: v, 61pDDC classification: 621 YAD

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Item type	Current library	Collection	Call number	Vol info	Status	Date due	Barcode	Item holds
M Tech DISSERTATION	LRC_JUIT	PROJECT REPORT SECTION	SPR 621 YAD (Browse shelf (Opens below))	Copy 1	Not for loan		SPM1338

Total holds: 0

Previous	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	Next
Previous	SPR 621 WAN Invisible Digital Image Watermarking using DCT and DWT	SPR 621 YAD 4-Channel Infra Red Remote Control	SPR 621 YAD Arbitrary Waveform Generator Based On FPGA	SPR 621 YAD FPGA Implementation of Low Complexity Decoder Using LDPC Codes	SPR 621 YAD Chaos Theory- Design of Chaotic Communication Systems	SPR 621 YAD Liver Ultrasound Image Segmentation Using Markov Random Field	SPR 624 AAT Structural Analysis and Design of A Multistory Building and Studying the Effect of Masonry Infills	Next

There are no comments on this title.

to post a comment.