Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits by Manoj Sachdev
Material type:
TextPublication details: New Delhi Springer (India) Pvt Ltd 2007Edition: 2nd edDescription: xxi, 328 pISBN: 9788184894295Subject(s): VLSI circuitsDDC classification: 621.395 SAC
Contents:
<p>Table of Contents:</p>
<p>1. Introd
| Item type | Current library | Collection | Call number | Vol info | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|
TEXT BOOK
|
LRC_JUIT Electronics & Communication Engineering | TEXTBOOK SECTION | 621.395 SAC (Browse shelf (Opens below)) | Copy 1 | Available | 024904 | ||
|
TEXT BOOK
|
LRC_JUIT Electronics & Communication Engineering | TEXTBOOK SECTION | 621.395 SAC (Browse shelf (Opens below)) | Copy 2 | Available | 025254 |
Total holds: 0
Browsing LRC_JUIT shelves, Shelving location: Electronics & Communication Engineering, Collection: TEXTBOOK SECTION Close shelf browser (Hides shelf browser)
|
|
|
|
|
|
|
||
| 621.395 ROY Low-power CMOS VLSI circuit design | 621.395 ROY Low-power CMOS VLSI circuit design | 621.395 RUS VHDL for logic synthesis | 621.395 SAC Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits | 621.395 SAC Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits | 621.395 SAK VLSI Design | 621.395 SAK VLSI Design |
<p>Table of Contents:</p>
<p>1. Introd
There are no comments on this title.