System-On-A-Chip Verification : methodology and Techniques Prakash Rashinkar
Material type:
TextPublication details: London Kluwer Academic Publishers 2000Description: xviii, 372pISBN: 0792372794Subject(s): System design | Computer software -- DevelopmentDDC classification: 621.395 RAS
| Item type | Current library | Collection | Call number | Vol info | Status | Date due | Barcode | Item holds |
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REFERENCE BOOK
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LRC_JUIT Electronics & Communication Engineering | REFERENCE SECTION | REF 621.395 RAS (Browse shelf (Opens below)) | Copy 1 | Not for loan | 015536 |
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| REF 621.395 NIC Power Constrained Testing of VLSI Circuits | REF 621.395 PER Precision Temperature Sensors in CMOS Technology | REF 621.395 RAM Digital VLSI Systems Design: a design manual for implementation of Projects on FPGAs and ASICs using Verilog | REF 621.395 RAS System-On-A-Chip Verification : methodology and Techniques | REF 621.395 ROS Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips | REF 621.395 ROT Fundamentals of Logic design | REF 621.395 ROY Low- Power CMOS VLSI Circuit Design |
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