OPAC_KOHA catalog › Details for: FPGA Implementation of Powet-Efficient Multiplier

Normal view MARC view ISBD view

FPGA Implementation of Powet-Efficient Multiplier by Manas Jain and Saksham

By: Jain, ManasContributor(s): SakshamMaterial type: Text

TextPublication details: Solan Jaypee University of Information Technology 2024Description: viii, 58pSubject(s): Electronics and Communication EngineeringDDC classification: 621 JAI

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Item type	Current library	Collection	Call number	Copy number	Status	Notes	Date due	Barcode	Item holds
B TECH PROJECT REPORTS	LRC_JUIT	PROJECT REPORT SECTION	621 JAI (Browse shelf (Opens below))	Copy 1	Not for loan	Guided by Shruti Jain_00195		SP2024184

Total holds: 0

Previous	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	Next
Previous	621 GUP Modelling and Simulation Of DDoS Attack Using Simevents	621 GUP Energy Efficient Street Lighting System	621 GUP Object Detection and Path Tracking	621 JAI FPGA Implementation of Powet-Efficient Multiplier	621 KAP Role of Transforms for Image Denoising	621 KAT Analysis and Design of Delectric Resonator Rod Antenna at Terahertz Frequency for Next-Generation Communication System	621 KAU Evaluation of Empirical Wavelet Transforms for Glaucoma Detection using Fundus Images	Next

There are no comments on this title.

to post a comment.