Computation structures Stephen A. Ward
Material type:
TextPublication details: Auckland McGraw-Hill 1989Description: xx, 789pISBN: 0262231395Subject(s): Logic Design | Computer -- circuits | Computer architectureDDC classification: 621.392 WAR
| Item type | Current library | Collection | Call number | Vol info | Status | Date due | Barcode | Item holds |
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REFERENCE BOOK
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LRC_JUIT Electronics & Communication Engineering | REFERENCE SECTION | REF 621.392 WAR (Browse shelf (Opens below)) | Copy 1 | Not for loan | 007266 |
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| REF 621.392 MUL CMOS Multichannel Single-Chip Receivers for Multi-gigabit Optical Data Communications | REF 621.392 PAD Design Through Verilog HDL | REF 621.392 SKA VHDL for Programmable Logic | REF 621.392 WAR Computation structures | REF 621.392 YAK Hardware Design and Petri Nets | REF 621.395 ATT PSpice and MATLAB for Electronics : an Integrated Approach | REF 621.395 BAD System-On-Chip for Real-Time Applications |
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