000 00535nam a2200157Ia 4500
008 180620b2017 xxu||||| |||| 00| 0 eng d
082 _a621 RAD
100 _aRadhika
245 _aFPGA Implementatiom of Arithmetic Operations Using Quaternary Signed Dight
_cRadhika
260 _aSolan {HP}
_bJaypee University of Information Technology
_c2017
300 _axiii,53p.
505 _aEnrolment No. 152016
650 _aElectronics & Communication Engineering
700 _aDr. Shruti Jain
906 _ace73b406a9fe5f787f798b2a552a34fa
999 _c51631
_d51631