000			00787nam a2200253Ia 4500
003			OSt
005			20230404113759.0
008			180620b2006 xxu||||| |||| 00| 0 eng d
020			_a0387255389
040			_cJUIT, Solan
082			_a621.392 BER
100			_aBergeron, Janick
245			_aVerification Methodology Manual for System Verilog _cby Janick Bergeron
260			_aNew York _bSpringer Verlag, Netherlands _c2006
300			_axvii, 503 p.
505			_a<p>Contents:</p> <p>1. Introduction</p
650			_aIntegrated circuits - Verification
650			_aVerilog (Computer Hardware Description Language)
700			_aNightingale, Andrew
700			_aHunter, Alan
700			_aCerny, Eduard
906			_ad4855ebfac100b2000e7945f3a74fc1e
942			_2ddc _cRB
999			_c52637 _d52637