000 00619 a2200205 4500
999 _c72544
_d72544
003 OSt
005 20191223153806.0
008 191223b ||||| |||| 00| 0 eng d
020 _a9789353062019
037 _cRs. 699.00
040 _cJUIT
082 _221
_a621.3815 MAN
100 _aMano, M.Morris
245 _aDigital Design: with an introduction to the verilog HDL, VHDL, and systemverilog
_cby M. Morris Mano and Michael D. Ciletti
250 _a6th ed.
260 _bPearson
_c2018
_aNoida
300 _a765p.
650 _vDigital Design
_vVHDL (Computer hardware description language)
942 _2ddc
_cTB