Processor Design: system-on-chip computing for asics and FPGAs Jari Nurmi
Material type:
TextPublication details: New York Springer Verlag, Netherlands 2007Description: xix, 525pISBN: 9781402055294Subject(s): Field programmable gate arrays | Application-specific integrated circuits | Systems on a chipDDC classification: 621.3815 NUR
| Item type | Current library | Collection | Call number | Vol info | Status | Date due | Barcode | Item holds |
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REFERENCE BOOK
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LRC_JUIT Computer Science & Engineering | REFERENCE SECTION | REF 621.3815 NUR (Browse shelf (Opens below)) | Copy 1 | Not for loan | 028695 |
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| REF 621.3815 CAR Metric-Driven Design Verification: an engineer's and executive's guide to first pass success | REF 621.3815 FAY Adaptive Techniques for Mixed Signal System on Chip | REF 621.3815 GUP SPARK: a parallelizing approach to the high-level synthesis of digital circuits | REF 621.3815 NUR Processor Design: system-on-chip computing for asics and FPGAs | REF 621.3815 SCH Introduction to Open Core Protocol: fastpath to system-on-chip design | REF 621.3815 TAN Wafer Level 3-D ICs Process Technology | REF 621.3815 YU Transient and Permanent Error Control for Networks-on-Chip |
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